koulib@sh.itjust.works to Linux@lemmy.mlEnglish · 7 days agoWhich new Protocol or Standard are you most excited about?message-squaremessage-square41fedilinkarrow-up167arrow-down12file-text
arrow-up165arrow-down1message-squareWhich new Protocol or Standard are you most excited about?koulib@sh.itjust.works to Linux@lemmy.mlEnglish · 7 days agomessage-square41fedilinkfile-text
minus-squarepizzaboi@lemm.eelinkfedilinkEnglisharrow-up17·7 days agoIs there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
minus-squaredeur@feddit.nllinkfedilinkarrow-up14·edit-26 days agoIn principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports. Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
minus-squarecaseyweederman@lemmy.calinkfedilinkarrow-up2·6 days agoARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
minus-squareMonkderVierte@lemmy.mllinkfedilinkarrow-up3·6 days agoAren’t they more like a hybrid instruction set and architecture?
Is there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
In principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.
Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
ARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
Aren’t they more like a hybrid instruction set and architecture?